The present invention relates generally to metal polishing and, particularly, to planarizing copper (Cu) and/or Cu alloy metallization in manufacturing semiconductor devices with reduced dishing and overpolish insensitivity. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures with improved reliability.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance and capacitance) interconnect pattern, particularly wherein submicron vias, contacts and conductive lines have high aspect rations imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an action region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric interlayer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section. The entire opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistivity than Al. In addition, Cu has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), titanium-titanium nitride (Tixe2x80x94TiN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier metals to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
In conventional CMP techniques, a wafer carrier assembly is in contact with a polishing pad in a CMP apparatus. The wafers are typically mounted on a carrier or polishing head which provides a controllable pressure urging the wafers against the polishing pad. The pad has a relative movement with respect to the wafer driven by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of each thin semiconductor wafer and the polishing pad while dispersing a polishing slurry containing abrasive particles in a reactive solution to effect both chemical activity and mechanical activity while applying a force between the wafer and a polishing pad. A different type of abrasive article from the above-mentioned abrasive slurry-type polishing pad is fixed abrasive article, e.g., fixed abrasive polishing pad. Such a fixed abrasive article typically comprises a backing sheet with a plurality of geometric abrasive composite elements adhered thereto.
It is extremely difficult to planarize a metal surface, particularly a Cu surface, as by CMP of a damascene inlay, with a high degree of surface planarity. A dense array of Cu features is typically formed in an interlayer dielectric, such as a silicon oxide layer, by a damascene technique wherein trenches are initially formed. A barrier layer, such as a Ta-containing layer e.g., Ta, TaN, is then deposited lining the trenches and on the upper surface of the silicon oxide interlayer dielectric. Cu or a Cu alloy is then deposited, as by electroplating, electroless plating, physical vapor deposition (PVD) at a temperature of about 50xc2x0 C. to about 150xc2x0 C. or chemical vapor deposition (CVD) at a temperature under about 200xc2x0 C., typically at a thickness of about 8,000 xc3x85 to about 18,000 xc3x85. CMP is then conducted to remove the Cu or Cu alloy overburden stopping on the barrier layer. Buffing is then conducted to remove the barrier layer, employing a mixture of a chemical agent and abrasive particles, leaving a Cu or the Cu alloy filling the damascene opening with an exposed surface. Overpolishing, as at about 10% to about 25%, is typically conducted beyond the time required to reach the interlayer dielectric, as determined by conventional end point detection techniques, e.g., to completely remove the barrier layer. For example, if 300 seconds of polishing are required to reach the targeted surface, 20% overpolishing would involve a total polishing time of 360 seconds. Conventional CMP techniques employing polishing pads utilizing slurries containing abrasive particles as well as CMP techniques employing fixed abrasive articles are characterized by excessive dishing sensitivity to overpolishing.
Dishing occurs wherein a portion of the surface of the inlaid metal of the interconnection formed in the groove in the interlayer dielectric is excessively polished resulting in one or more concavities or depressions. For example, adverting to FIG. 1, conductive lines 11 and 12 are formed by depositing a metal, such as Cu or a Cu alloy, in a damascene opening formed in interlayer dielectric 10, e.g., silicon dioxide. Subsequent to planarization, a portion of the inlaid metal 12 is depressed by an amount D referred to as the amount of dishing. For example, dishing occurring in metal lines, such as Cu or Cu alloy metal lines having a width of about 50 microns, generally exceeds 1,000 xc3x85 with as little overpolish as about 5% to about 10%.
Another phenomenon resulting from conventional planarization techniques is known as erosion which is characterized by excessive polishing of the layer not targeted for removal. For example, adverting to FIG. 2, metal line 21 and dense array of metal lines 22 are inlaid in interlayer dielectric 20. Subsequent to planarization, excessive polishing of the interlayer material results in erosion E.
Dishing disadvantageously results in a non-planar via that impairs the ability to print high resolution lines during subsequent photolithographic steps. Dishing can also cause the formation of shorts or open circuits in the metal interconnection formed thereover. Moreover, dishing increases with longer overpolishing than when overpolishing is conducted to ensure complete removal of the metal layer and/or barrier layer across the wafer surface.
Conventional CMP techniques employ abrasives, such as an abrasive-containing slurry for use on a conventional polishing pad. The use of abrasives disadvantageously results in a high degree of dishing and erosion, because of pressure transmitted through the abrasive particle to the metal. In addition, the use of abrasives significantly increases the cost of consumables, as abrasives and suspension agents, as well as post CMP effluent treatment, are expensive.
There exists a need for CMP methodology enabling the planarization of inlaid metal, particularly inlaid Cu metallization, with reduced dishing and insensitivity to overpolishing.
An aspect of the present invention is an efficient method of planarizing inlaid metals, such as Cu and Cu alloys, with significantly reduced dishing and significantly reduced sensitivity to overpolishing.
According to the present invention, the foregoing and other aspects are achieved in part by a method of removing at least part of a material, e.g., metal, from a substrate surface, the method comprising CMP the substrate surface using a composition having a pH and oxidation-reduction potential in the domain of passivation of the material.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprising planarizing a deposited Cu or Cu alloy layer on a dielectric layer by CMP employing a composition comprising: one or more chelating agents; one or more oxidizers, one or more corrosion inhibitors; one or more pH adjusting agents; and deionized water.
Embodiments of the present invention comprise CMP inlaid Cu metallization employing an abrasive-free polishing composition having a pH and oxidation-reduction potential in the domain of passivation of Cu and having a low static etching rate with respect to Cu. Embodiments of the present invention include polishing compositions comprising one or more chelating agents, such as ethylenediaminetetraacetic acid, ethylenediamine or methylformamide, one or more oxidizers, such as hydrogen peroxide, ferric nitrate or an iodate, one or more corrosion inhibitors, such as benzotriazole, mercaptobenzotriazole or 5-methyl-1-benzotriazole, one or more acids or bases sufficient to achieve a pH of about 3 to about 10, such as a pH of about 5 to about 8, e.g., an inorganic and/or organic acid, the remainder deionized water.
Additional aspects of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.